The present invention relates in general to the field of integrated circuits, and in particular to a method for scan chain initialization in integrated circuits.
As Moore's Law predicts, integrated computer chips are becoming more crowed due to complex circuitry. Scan chain is an efficient method for testing every flip-flop in an integrated computer chip prior to distribution, and helps to reduce the complexity of testing an integrated circuit with a considerably large portion of logic. A scan chain-enable pin may be integrated into an integrated circuit design. Testing is accomplished in a linear fashion according to latch type of each flip-flop, and a different clock domain may be designed to trigger each different latch type. Scan chain methods may include a partial scan that scans a portion of the total number of flip-flops, and a multiple scan chain that reduces test time by designing multiple scan chains in parallel.